(1) Field of the Invention
This invention relates to the formation of unlanded via holes through an inter-level dielectric layer for connection to underlying electrodes, and more specifically to methods of avoiding problems caused by oversize and mis-aligned via holes.
(2) Description of the Related Art
U.S. Pat. No. 5,451,543 to Woo et al. describes a method of forming contact via holes which allows the fabrication of unlanded vias having a substantially vertical sidewall profile. The method uses an etch stop layer.
U.S. Pat. No. 5,321,211 to Haslam et al. describes a method for forming contact vias in integrated circuits. The method describes the use of a single spacer on the electrode sidewalls.
U.S. Pat. No. 4,767,724 to Kim et al. describes a method which uses etch stops in the fabrication of unframed or borderless via openings.
U.S. Pat. No. 5,656,543 to Chung describes a method of forming borderless vias for interconnecting layers in a semiconductor device using a protective layer on the top of the underlying electrodes. An etch stop layer is used in forming the vias.
U.S. Pat. No. 5,317,192 to Chen et al. describes a method of forming a via hole using an amorphous silicon or oxide barrier layer on the sidewalls of the via hole.
U.S. Pat. No. 5,462,893 to Matsuoka et al. describes the use of an amorphous silicon layer as an etch stop layer.
U.S. Pat. No. 5,619,072 to Mehta describes a method of forming a multi-level semiconductor device with conducting vias utilizing an etch stop insulating material.
Stacked contacts and borderless contacts are discussed in the book "ULSI Technology", by C. Y. Chang and S. M. Sze, The McGraw-Hill Companies, Inc., 1996, pages 446-447.